US 12,464,815 B2
Fin cut in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication
Leonard P. Guler, Hillsboro, OR (US); Biswajeet Guha, Hillsboro, OR (US); Tahir Ghani, Portland, OR (US); Tsuan-Chung Chang, Portland, OR (US); and Sean Pursel, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 15, 2021, as Appl. No. 17/347,979.
Prior Publication US 2022/0399336 A1, Dec. 15, 2022
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/853 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/116 (2025.01); H10D 62/121 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 5 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a horizontal stack of semiconductor nanowire portions;
a dielectric gate spacer vertically over the horizontal stack of semiconductor nanowire portions;
a gate isolation structure laterally adjacent to a first side of the horizontal stack of semiconductor nanowire portions; and
a source or drain isolation structure laterally adjacent to a second side of the horizontal stack of semiconductor nanowire portions, wherein the source or drain isolation structure comprises a dielectric material, and wherein the horizontal stack of semiconductor nanowire portions is laterally between the source or drain isolation structure and the gate isolation structure.