	US 12,464,814 B2
	Method of manufacturing semiconductor devices and semiconductor devices
Kuan-Ting Pan, Taipei (TW); Kuo-Cheng Chiang, Zhubei (TW); Shi Ning Ju, Hsinchu (TW); Yi-Ruei Jihan, Keelung (TW); Wei Ting Wang, Taipei (TW); and Chih-Hao Wang, Baoshan Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 12, 2022, as Appl. No. 17/862,801.
Claims priority of provisional application 63/340,839, filed on May 11, 2022.
Prior Publication US 2023/0369327 A1, Nov. 16, 2023
Int. Cl. H10D 84/85 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01)

CPC H10D 84/851 (2025.01) [H10D 30/6735 (2025.01); H10D 64/017 (2025.01); H10D 84/0177 (2025.01); H10D 84/0179 (2025.01); H10D 84/0188 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/121 (2025.01); H10D 84/0193 (2025.01); H10D 84/85 (2025.01); H10D 84/853 (2025.01)]

20 Claims

18. A semiconductor device comprising:

a first gate-all-around field effect transistor (GAA FET) and a second GAA FET; and

a gate separation wall disposed between the first GAA FET and the second GAA FET and disposed on an isolation insulating layer, wherein:

the gate separation wall includes a first dielectric layer and a second dielectric layer embedded in the first dielectric layer, and

a gate electrode of at least one of the first GAA FET or the second GAA FET is in contact with an upper surface of the gate separation wall.