US 12,464,813 B2
Semiconductor device having hybrid middle of line contacts
Ruilong Xie, Niskayuna, NY (US); Su Chen Fan, Cohoes, NY (US); Veeraraghavan S. Basker, Schenectady, NY (US); Julien Frougier, Albany, NY (US); and Nicolas Loubet, Guilderland, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Oct. 19, 2021, as Appl. No. 17/504,765.
Prior Publication US 2023/0124681 A1, Apr. 20, 2023
Int. Cl. H01L 27/092 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/85 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/258 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A CMOS (complementary metal-oxide semiconductor) device comprising:
an n-channel metal-oxide semiconductor (NMOS) device;
a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material;
a first NMOS gate separated from a first PMOS gate by the second dielectric material;
a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the second NMOS gate and the second PMOS gate, the metal link disposed above the second dielectric material;
a first source/drain (S/D) contact disposed above the second dielectric material, the first S/D contact disposed in contact with both an NMOS S/D region and a PMOS S/D region; and
a second S/D contact disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a first single S/D region.