US 12,464,809 B2
Vertical field effect transistor with minimal contact to gate erosion
Su Chen Fan, Cohoes, NY (US); Christopher J. Waskiewicz, Rexford, NY (US); Yann Mignot, Slingerlands, NY (US); Jeffrey C. Shearer, Albany, NY (US); and Hemanth Jagannathan, Niskayuna, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 15, 2021, as Appl. No. 17/551,950.
Prior Publication US 2023/0187442 A1, Jun. 15, 2023
Int. Cl. H10D 84/83 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/834 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including at least one vertical fin extending from the substrate;
a bottom source/drain region beneath the at least one vertical fin;
a top source/drain region disposed above the at least one vertical fin;
a metal gate structure;
a contact coupled to the top source/drain region;
first and second contact spacers disposed on each side of the contact; and
an insulative layer disposed abutting a bottom surface of the first and second contact spacers, abutting sidewall portions of the top source/drain region and sidewall portions of the metal gate structure, and a top surface of the bottom source/drain region.