US 12,464,808 B2
Dummy cell designs for nanosheet devices
Praveen Raghavan, Cupertino, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 30, 2023, as Appl. No. 18/524,529.
Claims priority of provisional application 63/586,146, filed on Sep. 28, 2023.
Prior Publication US 2025/0113593 A1, Apr. 3, 2025
Int. Cl. H10D 84/83 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 89/00 (2025.01); H10D 89/10 (2025.01)
CPC H10D 84/83 (2025.01) [H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 89/00 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a substrate;
a plurality of active transistor cells having nanosheet fin regions with widths in a first direction of a horizontal dimension above the substrate and lengths in a second direction of the horizontal dimension, the second direction being perpendicular to the first direction, wherein the plurality of active transistor cells includes:
a first active transistor cell including a first nanosheet fin region having a first width; and
a second active transistor cell including a second nanosheet fin region having a second width different than the first width;
a plurality of dummy transistor cells having nanosheet fin regions with widths in the first direction and lengths in the second direction, wherein the plurality of dummy transistor cells includes:
a first dummy transistor cell positioned between the first active transistor cell and the second active transistor cell in the second direction, wherein the first dummy transistor cell includes a third nanosheet fin region with:
a first portion having a first interface with the first nanosheet fin region, the first portion having the first width; and
a second portion having a second interface with the second nanosheet fin region, the second portion having the second width;
a second dummy transistor cell positioned adjacent the first active transistor cell on an opposing side to the first dummy transistor cell in the second direction, wherein the second dummy transistor cell includes a fourth nanosheet fin region with a portion of the fourth nanosheet fin region interfacing the first nanosheet fin region and having the first width; and
an isolation structure between the first active transistor cell and the first dummy transistor cell, wherein the isolation structure extends lengthwise in the first direction over a part of the first portion of the third nanosheet fin region that is displaced in the second direction from the first interface.