	US 12,464,803 B2
	Multi-fin vertical field effect transistor and single-fin vertical field effect transistor on a single integrated circuit chip
Jeonghyuk Yim, Halfmoon, NY (US); and Kang Ill Seo, Springfield, VA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-do (KR)
Filed on Jan. 8, 2024, as Appl. No. 18/407,020.
Application 18/407,020 is a division of application No. 17/223,803, filed on Apr. 6, 2021, granted, now 11,901,240.
Claims priority of provisional application 63/138,598, filed on Jan. 18, 2021.
Prior Publication US 2024/0145313 A1, May 2, 2024
Int. Cl. H01L 21/20 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H10D 30/01 (2025.01); H10D 30/63 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)

CPC H10D 84/016 (2025.01) [H01L 21/3065 (2013.01); H01L 21/308 (2013.01); H10D 30/025 (2025.01); H10D 30/63 (2025.01); H10D 84/0128 (2025.01); H10D 84/0135 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)]

8 Claims

1. A method of forming a vertical field-effect transistor (VFET) device, the method comprising:

providing a substrate;

determining a number and positions of mask structures to be used to form 1^stfin structures for a plurality of single-fin VFETs and 2^ndfin structures for each of a plurality of multi-fin VFETs above the substrate;

depositing the mask structures above the substrate according to the determined number and positions;

patterning the substrate using the mask structures to form the 1^stfin structures and the 2^ndfin structures;

forming gate structures surrounding the 1^stfin structures, respectively, and forming a connected gate structure surrounding the 2^ndfin structures for each of the multi-fin VFETs;

forming a 1^stbottom source/drain region and a 1^sttop source/drain region vertically below and above each of the 1^stfin structure, respectively, and forming a 2^ndbottom source/drain region and a 2^ndtop source/drain region vertically below and above the 2^ndfin structures, respectively, and

forming an isolation structure to electrically disconnect neighboring two single-fin VFETs among the plurality of single-fin VFETs and electrically disconnect neighboring two multi-fin VFETs among the plurality of multi-fin VFETs,

wherein no isolation structure is formed between neighboring two 2^ndfin structures for a multi-fin VFET to electrically disconnect the connected gate structure surrounding the neighboring two 2^ndfin structures.