| CPC H10D 64/518 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/112 (2025.01); H10D 84/83 (2025.01)] | 20 Claims |
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1. A semiconductor circuit structure, comprising:
a semiconductor substrate having a first circuit region and a second circuit region;
active regions extended from the semiconductor substrate and surrounded by isolation features;
first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch;
second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second gate pitch greater than the first gate pitch; and
a dummy region surrounding the second transistors, wherein the dummy region includes first dummy gates configured next to the second gate stacks and having a third
gate pitch being equal to the second gate pitch, and
second dummy gates configured next to the first dummy gates and separated from the second gate stacks by the first dummy gates, the second dummy gates having a fourth gate pitch less than the second gate pitch.
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