| CPC H10D 64/111 (2025.01) [H10D 30/015 (2025.01); H10D 30/801 (2025.01); H10D 64/01 (2025.01); H10D 64/60 (2025.01)] | 26 Claims |

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1. A semiconductor device comprising:
a semiconductor substrate with an upper surface and a channel;
source and drain electrodes over the upper surface of the semiconductor substrate, wherein the source and drain electrodes are electrically coupled to the channel, and the channel extends between the source and drain electrodes;
a passivation layer over the upper surface of the semiconductor substrate and between the source and drain electrodes, wherein the passivation layer includes a lower passivation sub-layer over the upper surface of the semiconductor substrate, and an upper passivation sub-layer over the lower passivation sub-layer;
a first dielectric layer over the passivation layer;
a gate electrode over the upper surface of the semiconductor substrate between the source and drain electrodes, wherein the gate electrode includes a lower portion that extends through the first dielectric layer and the passivation layer; and
a conductive field plate adjacent to the gate electrode, wherein the conductive field plate includes a first portion with a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer, and an overhanging portion that extends over an upper surface of the first dielectric layer.
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