US 12,464,796 B2
Gate induced drain leakage reduction in FinFETs
Alexander Reznicek, Troy, NY (US); Takashi Ando, Eastchester, NY (US); Jingyun Zhang, Albany, NY (US); and Ruilong Xie, Niskayuna, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Nov. 14, 2023, as Appl. No. 18/508,367.
Application 17/479,250 is a division of application No. 16/740,958, filed on Jan. 13, 2020, granted, now 11,177,366, issued on Nov. 16, 2021.
Application 18/508,367 is a continuation of application No. 17/479,250, filed on Sep. 20, 2021, granted, now 11,855,180, issued on Dec. 26, 2023.
Prior Publication US 2024/0097006 A1, Mar. 21, 2024
Int. Cl. H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 62/822 (2025.01); H10D 62/832 (2025.01)
CPC H10D 64/017 (2025.01) [H10D 30/6211 (2025.01); H10D 62/151 (2025.01); H10D 62/832 (2025.01); H10D 62/8325 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
channel epitaxial wrap around layers present on each end of a channel region; and
a gate structure including a gate dielectric having end portions in direct contact with the channel epitaxial wrap around layer at said each end of the channel region, and a middle portion of the gate dielectric is in direct contact with a center portion of the channel region.