US 12,464,794 B2
Silicon carbide semiconductor device with improved avalanche resistance
Shunsuke Asaba, Himeji Hyogo (JP); and Hiroshi Kono, Himeji Hyogo (JP)
Assigned to Toshiba Electronic Devices & Storage Corporation, Kawasaki (JP); and Kabushiki Kaisha Toshiba, Kawasaki (JP)
Filed by TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP); and KABUSHIKI KAISHA TOSHIBA, Tokyo (JP)
Filed on Sep. 8, 2022, as Appl. No. 17/940,373.
Claims priority of application No. 2022-045801 (JP), filed on Mar. 22, 2022.
Prior Publication US 2023/0307502 A1, Sep. 28, 2023
Int. Cl. H10D 62/832 (2025.01); H10D 12/01 (2025.01); H10D 30/66 (2025.01)
CPC H10D 62/8325 (2025.01) [H10D 12/031 (2025.01); H10D 30/66 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a silicon carbide layer having a first face and a second face facing the first face;
a first silicon carbide region of a first conductive type provided in the silicon carbide layer, the first silicon carbide region including a first region, a second region, and a third region, the second region is disposed between the first region and the first face, the third region is disposed between the first region and the first face, a first-conductivity type impurity concentration in the second region is equal to or higher than a first-conductivity type impurity concentration in the first region, and a first-conductivity type impurity concentration in the third region is higher than the first-conductivity type impurity concentration in the second region;
a second silicon carbide region of a second conductive type provided in the silicon carbide layer and disposed between the first silicon carbide region and the first face, the second silicon carbide region including a fourth region and a fifth region, the fourth region is in contact with the second region, the fifth region is in contact with the third region, and a second-conductivity type impurity concentration in the fifth region is higher than a second-conductivity type impurity concentration in the fourth region;
a third silicon carbide region of a first conductive type provided in the silicon carbide layer and disposed between the second silicon carbide region and the first face;
a first gate electrode provided on a side of the first face of the silicon carbide layer, the first gate electrode extending in a first direction parallel to the first face, and the first gate electrode facing the second silicon carbide region on the first face;
a second gate electrode provided on the side of the first face of the silicon carbide layer, the second gate electrode extending in the first direction, the second gate electrode provided in a second direction with respect to the first gate electrode, the second direction being parallel to the first face and perpendicular to the first direction, and the second gate electrode facing the second silicon carbide region on the first face;
a first gate insulating layer provided between the second silicon carbide region and the first gate electrode;
a second gate insulating layer provided between the second silicon carbide region and the second gate electrode;
a first electrode provided on the side of the first face of the silicon carbide layer, the first electrode having a first portion provided between the first gate electrode and the second gate electrode and in contact with the second silicon carbide region and the third silicon carbide region; and
a second electrode provided on the side of the second face of the silicon carbide layer,
wherein the third region is in contact with the second region, and the fifth region is in contact with the fourth region.