US 12,464,791 B2
Semiconductor device
Masato Noborio, Nisshin (JP); Tomofumi Niibayashi, Nisshin (JP); and Jun Saito, Nisshin (JP)
Assigned to DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed by DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed on Feb. 22, 2023, as Appl. No. 18/172,590.
Claims priority of application No. 2022-034431 (JP), filed on Mar. 7, 2022; and application No. 2023-006761 (JP), filed on Jan. 19, 2023.
Prior Publication US 2023/0282705 A1, Sep. 7, 2023
Int. Cl. H10D 62/10 (2025.01); H10D 30/66 (2025.01); H10D 62/832 (2025.01)
CPC H10D 62/127 (2025.01) [H10D 30/668 (2025.01); H10D 62/8325 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate having a front surface and a rear surface opposite to each other, and having a cell region in which a semiconductor element is disposed;
a drift layer of a first conductivity type disposed on the front surface of the substrate, and having an impurity concentration lower than an impurity concentration of the substrate;
a first electrode disposed close to a surface of the drift layer;
a second electrode disposed close to the rear surface of the substrate;
a plurality of gate electrodes arranged apart from each other in one direction as an arrangement direction of the plurality of gate electrodes, the plurality of gate electrodes configured to turn on the semiconductor element and cause an electric current to flow between the first electrode and the second electrode in response to an applied voltage; and
a plurality of repeat regions of a second conductivity type disposed in the drift layer and arranged apart from each other in the arrangement direction of the plurality of gate electrodes, wherein
a plurality of center lines each of which passing through a center of each of the plurality of gate electrodes in the arrangement direction of the plurality of gate electrodes and extending in a thickness direction of the substrate is defined as a plurality of cell center lines,
a distance between adjacent two of the plurality of cell center lines in the arrangement direction of the plurality of gate electrodes is defined as a cell pitch,
a plurality of center lines each of which passing through a center of each of the plurality of repeat regions in the arrangement direction of the plurality of gate electrodes and extending in the thickness direction of the substrate is defined as a plurality of repeat center lines,
a distance between adjacent two of the plurality of repeat center lines in the arrangement direction of the plurality of gate electrodes is defined as a repeat pitch, and
the cell pitch is different from the repeat pitch.