US 12,464,781 B2
Memory cell, memory cell arrangement, and methods thereof
Stefan Ferdinand Müller, Dresden (DE)
Assigned to FERROELECTRIC MEMORY GMBH, Dresden (DE)
Filed by Ferroelectric Memory GmbH, Dresden (DE)
Filed on May 19, 2022, as Appl. No. 17/749,111.
Claims priority of provisional application 63/191,193, filed on May 20, 2021.
Prior Publication US 2022/0376114 A1, Nov. 24, 2022
Int. Cl. H10D 64/27 (2025.01); H10B 51/30 (2023.01); H10D 30/69 (2025.01)
CPC H10D 30/701 (2025.01) [H10B 51/30 (2023.02); H10D 64/513 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell comprising:
a semiconductor layer;
a recess disposed in the semiconductor layer;
a first source/drain region and a second source/drain region disposed in the semiconductor layer adjacent to the recess;
a floating gate disposed fully in the recess and a gate isolation disposed at least partially in the recess between the floating gate and the semiconductor layer;
a first electrode disposed over the floating gate and in electrical contact with the floating gate; wherein the first electrode is at least partially disposed in the recess;
a spontaneously polarizable layer disposed over the first electrode and a second electrode disposed over the spontaneously polarizable layer.