US 12,464,780 B2
Nonvolatile charge trap memory device having a high dielectric constant blocking region
Igor Polishchuk, Fremont, CA (US); Sagy Charel Levy, Zichron Yaakov (IL); and Krishnaswamy Ramkumar, San Jose, CA (US)
Assigned to LONGITUDE FLASH MEMORY SOLUTIONS LTD., Dublin (IE)
Filed by LONGITUDE FLASH MEMORY SOLUTIONS LTD., Dublin (IE)
Filed on Apr. 6, 2020, as Appl. No. 16/840,751.
Application 13/114,889 is a division of application No. 12/030,644, filed on Feb. 13, 2008, abandoned.
Application 16/840,751 is a continuation of application No. 15/252,059, filed on Aug. 30, 2016, granted, now 10,615,289.
Application 15/252,059 is a continuation of application No. 13/436,875, filed on Mar. 31, 2012, granted, now 9,431,549, issued on Aug. 30, 2016.
Application 13/436,875 is a continuation in part of application No. 13/114,889, filed on May 24, 2011, granted, now 8,860,122, issued on Oct. 14, 2014.
Claims priority of provisional application 61/007,566, filed on Dec. 12, 2007.
Prior Publication US 2020/0303563 A1, Sep. 24, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/69 (2025.01); B82Y 10/00 (2011.01); H10B 43/20 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01)
CPC H10D 30/691 (2025.01) [B82Y 10/00 (2013.01); H10B 43/20 (2023.02); H10D 30/025 (2025.01); H10D 30/031 (2025.01); H10D 30/0413 (2025.01); H10D 30/6728 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 30/69 (2025.01); H10D 30/693 (2025.01); H10D 62/122 (2025.01); H10D 64/037 (2025.01); H10D 64/685 (2025.01); H10D 64/691 (2025.01); H10D 64/693 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A nonvolatile memory transistor comprising:
a semiconductor substrate;
a gate structure;
a multi-layer blocking dielectric region adjacent the gate structure; and
a charge trapping region abutting the multi-layer blocking dielectric region, the charge trapping region having an oxygen-rich nitride layer and an oxygen-lean nitride layer, wherein the oxygen-lean nitride layer abuts the multi-layer blocking dielectric region, and the oxygen-rich nitride layer abuts the oxygen-lean nitride layer;
a tunnel oxide positioned such that the charge trapping region is located between the tunnel oxide and the multi-layer blocking dielectric region, wherein the oxygen-rich nitride layer abuts the tunnel oxide;
wherein the multi-layer blocking dielectric region includes a first dielectric layer comprising a silicon oxide and a second dielectric layer closest to the gate structure comprising a high K dielectric, wherein the first dielectric layer and the second dielectric layer are formed of different materials having different dielectric constants.