| CPC H10D 30/6757 (2025.01) [H10D 84/0126 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)] | 20 Claims |
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18. A semiconductor device comprising:
a substrate including a (110) silicon wafer;
an active pattern which includes a lower pattern extending lengthwise in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction on the substrate, the lower pattern including a protruding pattern protruding from the substrate in the second direction, and a first capping pattern on and contacting the protruding pattern;
a first gate structure and a second gate structure disposed on the lower pattern and spaced apart from each other in the first direction; and
a source/drain pattern which is disposed on the lower pattern and in contact with the plurality of sheet patterns,
wherein a thickness of the first capping pattern in a portion that overlaps the first gate structure is different from a thickness of the first capping pattern in a portion that overlaps the second gate structure,
wherein each of the plurality of sheet patterns includes an upper surface and a lower surface that are opposite in the second direction, and
wherein each of the upper surface and the lower surface of each of the plurality of sheet patterns has a (110) crystal plane.
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