| CPC H10D 30/6728 (2025.01) [H10B 12/05 (2023.02); H10B 12/315 (2023.02); H10D 30/673 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 99/00 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
a substrate;
a conductive line that extends in a first direction on the substrate;
an insulating pattern layer on the substrate that covers the conductive line, the insulating pattern layer having a trench that extends in a second direction that crosses the first direction, the trench having an extension portion that extends into the conductive line;
a channel layer on opposite sidewalls of the trench and connected to a region of the conductive line that is exposed by the extension portion of the trench;
a first gate electrode and a second gate electrode on the channel layer, and respectively arranged along the opposite sidewalls of the trench;
a gate insulating layer between the channel layer and the first and second gate electrodes;
a buried insulating layer between the first and second gate electrodes within the trench; and
a first contact and a second contact respectively buried in regions adjacent to the opposite sidewalls of the trench in the insulating pattern layer, and respectively connected to upper regions of the channel layer.
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