US 12,464,769 B2
Semiconductor device with epitaxial bridge feature and methods of forming the same
Ting-Yeh Chen, Hsinchu (TW); Wei-Yang Lee, Taipei (TW); and Chia-Pin Lin, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 8, 2022, as Appl. No. 17/883,234.
Application 17/883,234 is a division of application No. 17/127,343, filed on Dec. 18, 2020, granted, now 11,855,225.
Claims priority of provisional application 62/982,575, filed on Feb. 27, 2020.
Prior Publication US 2022/0384660 A1, Dec. 1, 2022
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H10D 30/01 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01)
CPC H10D 30/6713 (2025.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/28518 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/021 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/62 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a fin-shaped structure over a substrate and extending lengthwise along a direction, the fin-shaped structure comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
forming an isolation structure over the substrate to surround a lower portion of the fin-shaped structure;
forming a first dummy gate structure over a first channel region of the fin-shaped structure and a second dummy gate structure over a second channel region of the fin- shaped structure;
etching a source/drain region of the fin-shaped structure to form a source/drain trench and to expose sidewalls of the plurality of first semiconductor layers and the plurality of second semiconductor layers, the source/drain region being disposed between the first channel region and the second channel region;
recessing the source/drain trench such that sidewalls of the isolation structure are exposed in the source/drain trench;
after the recessing, depositing a bottom feature over a bottom surface of the source/drain trench;
after the depositing of the bottom feature, epitaxially growing a plurality of source/drain features extending between the plurality of first semiconductor layers under the first dummy gate structure and the plurality of first semiconductor layers under the second dummy gate structure; and
forming a source/drain contact to wrap around each of the plurality of source/drain features and to interface the bottom feature,
wherein each of the plurality of source/drain features comprises two edge portions and a middle portion disposed between the two edge portions along the direction,
wherein a thickness of the middle portion is smaller than a thickness of the two edge portions.