US 12,464,768 B2
Vertical semiconductor swiching elements with sense cell region
Takeshi Hagino, Kariya (JP); and Kenta Gouda, Kariya (JP)
Assigned to DENSO CORPORATION, Kariya (JP)
Filed by DENSO CORPORATION, Kariya (JP)
Filed on Dec. 28, 2022, as Appl. No. 18/147,065.
Application 18/147,065 is a continuation of application No. PCT/JP2021/024812, filed on Jun. 30, 2021.
Claims priority of application No. 2020-115972 (JP), filed on Jul. 3, 2020.
Prior Publication US 2023/0137999 A1, May 4, 2023
Int. Cl. H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 64/27 (2025.01)
CPC H10D 30/669 (2025.01) [H10D 62/124 (2025.01); H10D 62/213 (2025.01); H10D 64/513 (2025.01)] 5 Claims
OG exemplary drawing
 
1. A semiconductor device in which vertical semiconductor switching elements having a same structure are provided in a main cell region and a sense cell region, the semiconductor device comprising:
a drift layer of a first conductivity type;
a channel layer of a second conductivity type, arranged on the drift layer;
a first impurity region of the first conductivity type, arranged at a surface layer portion in the channel layer, the first impurity region having an impurity concentration higher than that of the drift layer;
a gate insulating film configured to cover the channel layer in an area between the first impurity region and the drift layer;
a gate electrode layer arranged in stripe-like plural lines extending in one direction and provided at a surface of the gate insulating film to form a channel region;
a second impurity region of the first or second conductivity type, arranged on an opposite side of the channel layer with the drift layer interposed therebetween, the second impurity region having an impurity concentration higher than that of the drift layer;
an upper electrode electrically connected to the first impurity region and the channel layer; and
a lower electrode electrically connected to the second impurity region, wherein
the sense cell region is defined as a quadrangular region surrounding an operating region of the semiconductor switching element formed as a sense cell, with (i) a lateral dimension of the sense cell region defined along the one direction of the main cell region, and (ii) a longitudinal dimension of the sense cell region defined along a longitudinal direction that is orthogonal to the lateral direction of the sense cell region,
the longitudinal dimension of the sense cell region is equal to or greater than the lateral dimension of the sense cell region,
each of the gate electrode layers continually extends in the one direction over the sense cell region and the main cell region, in an area where the sense cell region is provided, and
a pitch of the gate electrode layers arranged in stripes in the sense cell region is larger than a pitch of the gate electrode layers arranged in stripes in the main cell region.