| CPC H10D 30/665 (2025.01) [H10D 62/106 (2025.01); H10D 62/8325 (2025.01)] | 21 Claims |
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1. A semiconductor device including an active region in which a main current flows in a thickness direction of a semiconductor substrate, wherein
the semiconductor substrate is divided into an inner region in which the active region is provided and an outer region surrounding the inner region,
the semiconductor device includes
a semiconductor layer of a first conductivity type,
a termination well region of a second conductivity type being a conductivity type different from the first conductivity type, the termination well region being selectively provided in an upper layer portion of the semiconductor layer to surround the inner region in plan view,
an impurity region of the first or second conductivity type, the impurity region being selectively provided in an upper layer portion of the termination well region,
a front surface electrode being provided on a side of a second main surface of the semiconductor substrate, the second main surface being opposite to a first main surface of the semiconductor substrate,
a back surface electrode being provided on the first main surface,
an insulation film being provided to partially cover a top of the termination well region,
an outer peripheral wire layer surrounding the inner region in the plan view, at least a part of the outer peripheral wire layer being provided on the insulation film, and
an interlayer insulation film at least covering the insulation film and the outer peripheral wire layer,
the termination well region extends from a boundary between the inner region and the outer region to the outer region,
the front surface electrode is provided from the inner region to a top of the interlayer insulation film, and is connected to the impurity region through a first contact hole passing through the interlayer insulation film to reach the impurity region,
the outer peripheral wire layer is provided to be separated away from the gate electrode provided in the inner region and led out to the outer region, and the outer peripheral wire layer is provided so that an outer peripheral end portion of
the outer peripheral wire layer on an outer peripheral side being opposite to the inner region in the plan view is located on an inner peripheral side with respect to an outer peripheral end portion of the termination well region being opposite to the inner region in the plan view, and is located on an outer side with respect to a position below an end portion of the front surface electrode on the interlayer insulation film.
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