| CPC H10D 30/65 (2025.01) [H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/32133 (2013.01); H10D 30/0281 (2025.01); H10D 62/393 (2025.01); H10D 64/111 (2025.01)] | 9 Claims |
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1. An LDMOS device, comprising:
a substrate, which is of a first dopant type;
an epitaxial layer, which is of the first dopant type and is formed on an upper surface of the substrate;
a gate structure disposed on an upper surface of the epitaxial layer;
a well region, which is of the first dopant type, and a drift region, which is of a second dopant type, wherein the well region and the drift region are disposed in the epitaxial layer, wherein the first dopant type and the second dopant type contain opposite dopants;
a source region, which is of the second dopant type and is disposed within the well region;
a drain region, which is of the first dopant type and is disposed within the drift region;
a first insulating layer, covering an upper surface and two sidewalls of the gate structure and the upper surface of the epitaxial layer;
a first conducting channel, extending through the first insulating layer, the source region, and the epitaxial layer before reaching the substrate, wherein the first conducting channel is in contact with a side surface and an upper surface of the source region, wherein the first conducting channel electrically connects the source region and the substrate;
a second insulating layer, disposed above the first conducting channel and the first insulating layer;
a second conducting channel, extending to an upper surface of the drain region;
a drain electrode, connected to the drain region by the second conducting channel;
a gate electrode, connected to the gate structure; and
a source electrode, disposed on a surface of the substrate facing away from the epitaxial layer.
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