US 12,464,761 B2
LOCOS fillet for drain reduced breakdown in high voltage transistors
Martin B. Mollat, Gainesville, TX (US); Henry L. Edwards, Garland, TX (US); and Alexei Sadovnikov, Sunnyvale, CA (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 30, 2022, as Appl. No. 18/072,201.
Prior Publication US 2024/0178318 A1, May 30, 2024
Int. Cl. H10D 30/01 (2025.01); H01L 21/762 (2006.01); H10D 30/60 (2025.01); H10D 30/65 (2025.01); H10D 64/00 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/603 (2025.01) [H01L 21/76202 (2013.01); H10D 30/0221 (2025.01); H10D 30/65 (2025.01); H10D 64/111 (2025.01); H10D 64/112 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01); H10D 30/601 (2025.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a source region and a drain region spaced apart and extending into a semiconductor layer having a first conductivity type, the source region and the drain region having an opposite second conductivity type;
a gate electrode extending between the source and the drain regions; and
a dielectric layer between the gate electrode and the semiconductor layer, the dielectric layer including a first portion having a first thickness in contact with the semiconductor layer, and a second portion with a greater second thickness over the semiconductor layer, a lateral perimeter of the second portion surrounding the source region and including:
a first edge having a first linear segment extending over the semiconductor layer and between the source region and the drain region along a first direction; and
a second edge having a second linear segment extending over the semiconductor layer along a different second direction; and
a fillet of the second portion connecting the first linear segment and the second linear segment of the lateral perimeter.