US 12,464,759 B2
High electron mobility transistors having reduced drain current drift and methods of fabricating such devices
Kyle Bothe, Cary, NC (US); Chris Hardiman, Cary, NC (US); Elizabeth Keenan, Cary, NC (US); Jia Guo, Apex, NC (US); Fabian Radulescu, Chapel Hill, NC (US); and Scott Sheppard, Chapel Hill, NC (US)
Assigned to MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Aug. 18, 2022, as Appl. No. 17/890,453.
Prior Publication US 2024/0063300 A1, Feb. 22, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H10D 1/60 (2025.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01); H10D 64/23 (2025.01); H10D 64/68 (2025.01)
CPC H10D 30/475 (2025.01) [H10D 62/8503 (2025.01); H10D 64/251 (2025.01); H10D 30/015 (2025.01); H10D 64/693 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A high electron mobility transistor, comprising:
a semiconductor layer structure that includes a channel layer and a barrier layer on the channel layer;
a source contact on the semiconductor layer structure;
a drain contact on the semiconductor layer structure;
a gate contact on the semiconductor layer structure between the source contact and the drain contact;
a multi-layer passivation structure on the semiconductor layer structure between the source contact and the drain contact, the multi-layer passivation structure including a plurality of layers that include at least a first silicon nitride layer and a second silicon nitride layer that has a material composition that is different than a material composition of the first silicon nitride layer; and
a spacer passivation layer on sidewalls of both the first silicon nitride layer and the second silicon nitride layer,
wherein a material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure,
wherein a bottom surface of the spacer passivation layer is coplanar with a bottom surface of the gate contact,
wherein the first silicon nitride layer directly contacts the barrier layer and the second silicon nitride layer is on the first silicon nitride layer opposite the barrier layer, where the second silicon nitride layer is more silicon-rich than the first silicon nitride layer, and
wherein the multi-layer passivation structure further comprises a third silicon nitride layer on the second silicon nitride layer opposite the first silicon nitride layer, where the third silicon nitride layer is more silicon-rich than the first silicon nitride layer.
 
5. A high electron mobility transistor, comprising:
a semiconductor layer structure that includes a channel layer and a barrier layer on the channel layer;
a source contact on the semiconductor layer structure;
a drain contact on the semiconductor layer structure;
a gate contact on the semiconductor layer structure between the source contact and the drain contact;
a multi-layer passivation structure on the semiconductor layer structure between the source contact and the drain contact, the multi-layer passivation structure including a plurality of layers that include at least a first silicon nitride layer and a second silicon nitride layer that has a material composition that is different than a material composition of the first silicon nitride layer; and
a spacer passivation layer on sidewalls of both the first silicon nitride layer and the second silicon nitride layer,
wherein a material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure,
wherein the first silicon nitride layer directly contacts the barrier layer and the second silicon nitride layer is on the first silicon nitride layer opposite the barrier layer, where the second silicon nitride layer is more silicon-rich than the first silicon nitride layer,
wherein the multi-layer passivation structure further comprises a third silicon nitride layer on the second silicon nitride layer opposite the first silicon nitride layer, where the third silicon nitride layer is more silicon-rich than the first silicon nitride layer, and
wherein the spacer passivation layer comprises a silicon-rich silicon nitride layer that is more silicon-rich than all three of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer.
 
6. A high electron mobility transistor, comprising:
a semiconductor layer structure that includes a channel layer and a barrier layer on the channel layer;
a source contact on the semiconductor layer structure;
a drain contact on the semiconductor layer structure;
a gate contact on the semiconductor layer structure between the source contact and the drain contact;
a multi-layer passivation structure on the semiconductor layer structure between the source contact and the drain contact, the multi-layer passivation structure including a plurality of layers that include at least a first silicon nitride layer and a second silicon nitride layer that has a material composition that is different than a material composition of the first silicon nitride layer; and
a spacer passivation layer on sidewalls of both the first silicon nitride layer and the second silicon nitride layer,
wherein a material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure,
wherein a bottom surface of the spacer passivation layer is coplanar with a bottom surface of the gate contact,
wherein the spacer passivation layer comprises an inner side that faces the multi-layer passivation structure and an outer side that is opposite the inner side, the outer side having a concave profile.
 
7. A high electron mobility transistor, comprising:
a semiconductor layer structure that includes a channel layer and a barrier layer on the channel layer:
a source contact on the semiconductor layer structure;
a drain contact on the semiconductor layer structure;
a gate contact on the semiconductor layer structure between the source contact and the drain contact;
a multi-layer passivation structure on the semiconductor layer structure between the source contact and the drain contact, the multi-layer passivation structure including a plurality of layers that include at least a first silicon nitride layer and a second silicon nitride layer that has a material composition that is different than a material composition of the first silicon nitride layer; and
a spacer passivation layer on sidewalls of both the first silicon nitride layer and the second silicon nitride layer,
wherein a material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure,
wherein a bottom surface of the spacer passivation layer is coplanar with a bottom surface of the gate contact,
wherein a longitudinal axis of the gate contact extends on the barrier layer in a first direction, the multi-layer passivation structure extends on the barrier layer a first distance in a second direction that is perpendicular to the first direction, and the spacer passivation layer extends on the barrier layer a second distance in the second direction that is less than 5 percent the first distance.
 
8. A high electron mobility transistor, comprising:
a semiconductor layer structure that includes a channel layer and a barrier layer on the channel layer;
a source contact on the semiconductor layer structure;
a drain contact on the semiconductor layer structure;
a gate contact on the semiconductor layer structure between the source contact and the drain contact;
a multi-layer passivation structure on the semiconductor layer structure between the source contact and the drain contact, the multi-layer passivation structure including a plurality of layers that include at least a first silicon nitride layer and a second silicon nitride layer that has a material composition that is different than a material composition of the first silicon nitride layer; and
a spacer passivation layer on sidewalls of both the first silicon nitride layer and the second silicon nitride layer,
wherein a material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure,
wherein a bottom surface of the spacer passivation layer is coplanar with a bottom surface of the gate contact,
wherein a quiescent drain current of the high electron mobility transistor is within 10 percent of a peak drain current of the high electron mobility transistor.