US 12,464,754 B2
Metal oxide semiconductor device and method for manufacturing the same
He Sun, Hangzhou (CN); and Jiakun Wang, Hangzhou (CN)
Assigned to Silicon-Magic Semiconductor Technology (Hangzhou) Co., Ltd., Hangzhou (CN)
Filed by Silicon-Magic Semiconductor Technology (Hangzhou) Co., Ltd., Hangzhou (CN)
Filed on Sep. 26, 2022, as Appl. No. 17/952,778.
Claims priority of application No. 202111427488.2 (CN), filed on Nov. 29, 2021.
Prior Publication US 2023/0170401 A1, Jun. 1, 2023
Int. Cl. H10D 30/66 (2025.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H10D 30/01 (2025.01); H10D 62/17 (2025.01); H10D 64/27 (2025.01)
CPC H10D 30/0291 (2025.01) [H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H10D 30/66 (2025.01); H10D 62/314 (2025.01); H10D 64/516 (2025.01); H10D 64/519 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A metal oxide semiconductor device, comprising:
a semiconductor substrate, comprising active regions and gate regions disposed on an upper surface of the semiconductor substrate, wherein each of the active regions is surrounded by two or more of the gate regions, wherein the gate regions form a grid, comprising a plurality of gate intersections which are formed from intersecting gate regions;
a patterned field oxide layer, wherein the patterned field oxide layer is configured to overlap with one of the plurality of gate intersections;
wherein the semiconductor substrate further comprises ion-implanted regions, wherein the ion-implanted regions comprise first JFET implantation regions and second JFET implantation regions;
wherein each of the first JFET implantation regions is configured to be underneath one of the plurality of gate intersections, wherein an orthogonal projection of each of the first JFET implantation regions and an orthogonal projection of said patterned field oxide layer onto the semiconductor substrate do not overlap; and
wherein each of the second JFET implantation regions is configured to be underneath non-intersecting gate regions.