US 12,464,751 B2
Contact plugs and methods forming same
Kuo-Hua Pan, Hsinchu (TW); Je-Wei Hsu, Hsinchu (TW); Hua Feng Chen, Hsinchu (TW); Jyun-Ming Lin, Hsinchu (TW); Chen-Huang Peng, Hsinchu (TW); Min-Yann Hsieh, Kaohsiung (TW); and Java Wu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 8, 2023, as Appl. No. 18/504,745.
Application 16/206,071 is a division of application No. 15/610,981, filed on Jun. 1, 2017, granted, now 10,516,030, issued on Dec. 24, 2019.
Application 18/504,745 is a continuation of application No. 17/181,607, filed on Feb. 22, 2021, granted, now 11,862,708.
Application 17/181,607 is a continuation of application No. 16/206,071, filed on Nov. 30, 2018, granted, now 10,930,752, issued on Feb. 23, 2021.
Claims priority of provisional application 62/443,885, filed on Jan. 9, 2017.
Prior Publication US 2024/0072155 A1, Feb. 29, 2024
Int. Cl. H01L 23/485 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01); H01L 21/285 (2006.01)
CPC H10D 30/0212 (2025.01) [H01L 21/31144 (2013.01); H01L 21/76831 (2013.01); H01L 23/485 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 64/62 (2025.01); H01L 21/28518 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a substrate;
two conductive features positioned apart from each other over the substrate;
a graded porous dielectric structure positioned between the two conductive features, wherein the graded porous dielectric structure comprises:
a first portion having a first porosity; and
a second portion having a second porosity, wherein the second porosity is higher than the first porosity; and
a dielectric layer positioned between one of the two conductive features and the graded porous dielectric structure, wherein the dielectric layer comprises a gate spacer, and the gate spacer comprises:
an L-shaped layer comprising a horizontal leg and a vertical leg connecting to the horizontal leg, wherein the vertical leg contacts the graded porous dielectric structure; and
an outer spacer overlapping the horizontal leg, wherein the outer spacer contacts the vertical leg to form a vertical interface.