US 12,464,749 B2
Power semiconductor device
Jan Vobecky, Lenzburg (CH); and Umamaheswara Vemulapati, Windisch (CH)
Assigned to HITACHI ENERGY LTD, Zürich (CH)
Appl. No. 18/023,982
Filed by Hitachi Energy Ltd, Zürich (CH)
PCT Filed Aug. 19, 2021, PCT No. PCT/EP2021/073039
§ 371(c)(1), (2) Date Feb. 28, 2023,
PCT Pub. No. WO2022/048919, PCT Pub. Date Mar. 10, 2022.
Claims priority of application No. 20194292 (EP), filed on Sep. 3, 2020.
Prior Publication US 2023/0317818 A1, Oct. 5, 2023
Int. Cl. H10D 18/00 (2025.01); H10D 18/01 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01)
CPC H10D 18/01 (2025.01) [H10D 18/00 (2025.01); H10D 62/126 (2025.01); H10D 62/148 (2025.01); H10D 64/233 (2025.01); H10D 64/291 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A power semiconductor device comprising a semiconductor wafer having a first main side and a second main side opposite to the first main side (1), the semiconductor wafer comprising a plurality of parallel thyristor cells, wherein each thyristor cell comprises in an order from the first main side to the second main side:
(a) a cathode electrode and a gate electrode arranged on the first main side;
(b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode;
(c) a first base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the first base layer and forms a first p-n junction between the first base layer and the cathode region;
(d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer;
(e) an anode layer of the second conductivity type separated from the first base layer by the second base layer;
wherein the gate electrode forms an ohmic contact with the first base layer, and an anode electrode is arranged on the second main side and forms an ohmic contact with the anode layer;
wherein the gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts,
wherein the cathode regions are of hexagonal shape, and the cathode layers comprise cathode short areas of the second conductivity type connecting the cathode electrodes with the first base layers,
wherein the cathode short areas are of polygonal shape or circular shape or stripe shape and the cathode short areas are placed along a hexagonal gate-cathode boundary within the hexagonal cathode region.