US 12,464,746 B1
Isolation stack for a bipolar transistor and related methods
Jacob M. DeAngelis, Essex Junction, VT (US); Uppili S. Raghunathan, Essex Junction, VT (US); Steven M. Shank, Jericho, VT (US); Sarah A. McTaggart, Essex Junction, VT (US); Megan Elizabeth Lydon-Nuhfer, Essex Junction, VT (US); and Cameron Luce, Colchester, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Nov. 13, 2024, as Appl. No. 18/945,645.
Int. Cl. H10D 10/80 (2025.01); H10D 10/01 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01)
CPC H10D 10/821 (2025.01) [H10D 10/021 (2025.01); H10D 62/115 (2025.01); H10D 62/133 (2025.01); H10D 62/137 (2025.01); H10D 62/177 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A structure comprising:
a first isolation layer on a subcollector, wherein a first air gap is between the first isolation layer and a collector of a bipolar transistor (BT);
a second isolation layer on the first isolation layer and adjacent an intrinsic base of the BT; and
a third isolation layer on the second isolation layer, vertically between the second isolation layer and an extrinsic base of the BT, wherein a second air gap is adjacent the third isolation layer and below the extrinsic base, and wherein the second isolation layer defines a physical boundary between the first air gap and the second air gap.