	US 12,464,741 B2
	Stacked high-blocking InGaAs semiconductor power diode
Thorsten Wierzkowski, Heilbronn (DE); and Daniel Fuhrmann, Heilbronn (DE)
Assigned to Azur Space Solar Power GmbH, Heilbronn (DE)
Filed by AZUR SPACE Solar Power GmbH, Heilbronn (DE)
Filed on Mar. 22, 2021, as Appl. No. 17/209,151.
Claims priority of application No. 10 2020 001 843.2 (DE), filed on Mar. 20, 2020.
Prior Publication US 2021/0296509 A1, Sep. 23, 2021
Int. Cl. H10D 8/00 (2025.01); H10D 8/01 (2025.01); H10D 62/60 (2025.01); H10D 62/85 (2025.01)

CPC H10D 8/422 (2025.01) [H10D 8/043 (2025.01); H10D 62/60 (2025.01); H10D 62/85 (2025.01)]

25 Claims

1. A high-blocking 111-V semiconductor power diode comprising:

a highly doped first semiconductor contact area of a first conductivity type having a dopant concentration of at least 1·10¹⁸cm-³and having a first lattice constant;

a low-doped semiconductor drift region of the first conductivity type or of a second conductivity type arranged beneath the first semiconductor contact area having a dopant concentration of 8·10¹¹-1·10¹⁵cm-³and having the first lattice constant and a layer thickness of 10 μm-200 μm;

a highly doped second semiconductor contact area of the second conductivity type arranged beneath the semiconductor drift region having a dopant concentration of at least 5·10¹⁷cm-³and having a second lattice constant;

a highly doped metamorphic buffer layer sequence disposed between the semiconductor drift region and the second semiconductor contact area, the metamorphic buffer layer sequence having the first lattice constant on an upper surface facing the semiconductor drift region and the second lattice constant on a lower surface facing the second semiconductor contact area;

a first metallic terminal contact layer, which is formed at least in regions and is materially bonded with an upper surface of the first semiconductor contact area; and

a second metallic terminal contact layer, which is formed at least in regions and is arranged beneath a lower surface of the second semiconductor contact area,

wherein at least the first semiconductor contact area forms a core stack having an upper surface, a lower surface, and a side face extending from the upper surface to the lower surface,

wherein the 111-V semiconductor power diode has a dielectric frame region enclosing the core stack along the side face, the dielectric frame region having an upper surface at an uppermost portion of the dielectric frame region and a lower surface at a lowermost portion of the dielectric frame region, and the upper surface of the dielectric frame region being directly over the lower surface of the dielectric frame region,

wherein the upper surface of the core stack terminates with the upper surface of the dielectric frame region or forms a first step to the upper surface of the dielectric frame region,

wherein the lower surface of the core stack terminates with the lower surface of the dielectric frame region or forms a second step to the lower surface of the dielectric frame region, and

wherein semiconductor areas of the 111-V semiconductor power diode arranged beneath the first semiconductor contact area are each either included in the core stack or form a carrier portion, and

wherein the carrier portion is arranged beneath the core stack and the dielectric frame region and is provided with a common lower surface, which is formed by the lower surface of the dielectric frame region and the lower surface of the core stack, and are materially bonded.