US 12,464,740 B2
Semiconductor device and module
Hiroshi Matsubara, Nagaokakyo (JP); Masatomi Harada, Nagaokakyo (JP); and Takeshi Kagawa, Nagaokakyo (JP)
Assigned to Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Aug. 3, 2022, as Appl. No. 17/880,113.
Application 17/880,113 is a continuation of application No. PCT/JP2021/005626, filed on Feb. 16, 2021.
Claims priority of application No. 2020-024563 (JP), filed on Feb. 17, 2020.
Prior Publication US 2022/0376036 A1, Nov. 24, 2022
Int. Cl. H10D 1/68 (2025.01); H01G 4/008 (2006.01); H01G 4/10 (2006.01); H01G 4/232 (2006.01); H01G 4/30 (2006.01)
CPC H10D 1/696 (2025.01) [H01G 4/008 (2013.01); H01G 4/10 (2013.01); H01G 4/232 (2013.01); H01G 4/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate having a first main surface and a second main surface opposite to each other in a thickness direction;
a circuit layer disposed on the first main surface of the semiconductor substrate and including:
a first electrode layer disposed on a side of the semiconductor substrate,
a second electrode layer disposed above the first electrode layer,
a dielectric layer interposed between the first and second electrode layers in the thickness direction,
a first outer electrode electrically connected to the first electrode layer and extending to a surface of the circuit layer on a side opposite the semiconductor substrate, and
a second outer electrode electrically connected to the second electrode layer and extending to the surface of the circuit layer on the side opposite from the semiconductor substrate; and
a first resin body that protrudes from the surface of the circuit layer and in between the first and second outer electrodes in a plan view of the surface of the circuit layer,
wherein, in a sectional view, a tip end of the first resin body on the side opposite the semiconductor substrate is positioned higher than respective tip ends of the first and second outer electrodes on the side opposite from the semiconductor substrate,
wherein the first outer electrode overlaps the first electrode layer in the plan view of the surface of the circuit layer, and
wherein the second outer electrode overlaps the second electrode layer in the plan view of the surface of the circuit layer.