US 12,464,738 B2
Integrated chip including a device with a reduced surface field region
Liang-Yu Su, Yunlin County (TW); Chih-Wen Yao, Hsinchu (TW); Hsiao-Chin Tuan, Ju Dong County (TW); and Ming-Ta Lei, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 2, 2024, as Appl. No. 18/624,264.
Application 17/324,402 is a division of application No. 16/434,381, filed on Jun. 7, 2019, granted, now 11,018,266, issued on May 25, 2021.
Application 18/624,264 is a continuation of application No. 17/324,402, filed on May 19, 2021, granted, now 11,978,810.
Claims priority of provisional application 62/749,188, filed on Oct. 23, 2018.
Prior Publication US 2024/0250188 A1, Jul. 25, 2024
Int. Cl. H10D 1/64 (2025.01); H10D 1/00 (2025.01); H10D 62/10 (2025.01); H10D 84/00 (2025.01)
CPC H10D 1/64 (2025.01) [H10D 1/045 (2025.01); H10D 62/109 (2025.01); H10D 84/215 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip comprising:
a first doped region in a substrate and comprising a first doping type;
a gate structure over the first doped region;
a pair of contact regions in the substrate on opposing sides of the gate structure and comprising the first doping type, wherein the first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions; and
a second doped region in the substrate and along a bottom of the first doped region, wherein the second doped region comprises a second doping type opposite the first doping type, wherein a top of the second doped region contacts or is vertically above a bottom of the pair of contact regions.