| CPC H10D 1/043 (2025.01) [H01L 21/76838 (2013.01); H01L 23/5226 (2013.01); H10D 1/716 (2025.01)] | 15 Claims |
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1. A semiconductor device manufacturing method, the method comprising:
providing a logic region and a capacitor region on a substrate;
forming a pre-metal dielectric film on the substrate;
forming a first metal line on the pre-metal dielectric film in the logic region; forming a first inter-metal dielectric film on the first metal line;
simultaneously forming a second metal line and a bottom electrode on the first inter- metal dielectric film; forming a second inter-metal dielectric film on the second metal line and the bottom electrode;
forming a third metal line on the second inter-metal dielectric film in the logic region;
forming a third inter-metal dielectric film on the third metal line;
forming a top metal layer on the third inter-metal dielectric film;
patterning the top metal layer to simultaneously form a top metal line in the logic region and a top electrode in the capacitor region;
forming a first passivation film having a first thickness on the top metal line and the top electrode;
performing a chemical mechanical polishing (CMP) process to flatten the first passivation film;
performing a first etch-back process to etch the first passivation film, the top metal line, and the top electrode;
performing a second etch-back process, affer exposure of the top metal line and the top electrode, to etch the first passivation film, the exposed top metal line, and the exposed top electrode to:
round or slope top comers of the top metal line and the top electrode, and
reduce the thickness of the first passivation film to a second thickness that is less than the first thickness; and
forming a second passivation film over the reduced first passivation film, the top metal line, and the top electrode,
wherein the second passivation film is in direct contact with the rounded or sloped top corners of the top metal line and the top electrode.
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