| CPC H10B 61/00 (2023.02) [G11C 11/1675 (2013.01)] | 11 Claims |
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1. A semiconductor storage apparatus, comprising:
a plurality of memory cells, wherein each of the plurality of the memory cells includes:
a respective magnetization reversal memory device of a plurality of magnetization reversal memory devices, and
a respective first switch device of a plurality of first switch devices, wherein the respective first switch device is configured to control a current to flow to the respective magnetization reversal memory device; and
a control circuit configured to:
perform a writing control to output a first pulse and a second pulse to the respective magnetization reversal memory device, wherein
the writing control is based on an asymmetric property of a writing error rate curve line with respect to a writing voltage of the respective magnetization reversal memory device,
the first pulse is associated with a first state of the writing control,
the second pulse is associated with a second state of the writing control, and
the first pulse corresponds to a first pulse width (Wa) and the second pulse corresponds to a second pulse width (Wb); and
control an ON period of the respective first switch device such that the Wa is different from the Wb.
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