US 12,464,731 B2
Layered bottom electrode dielectric for embedded MRAM
Ashim Dutta, Clifton Park, NY (US); Michael Rizzolo, Delmar, NY (US); Jon Slaughter, Slingerlands, NY (US); Chih-Chao Yang, Glenmont, NY (US); and Theodorus E. Standaert, Clifton Park, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Dec. 14, 2021, as Appl. No. 17/644,098.
Prior Publication US 2023/0189534 A1, Jun. 15, 2023
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/00 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device including a logic area and a memory area, the method comprising:
forming a first dielectric cap layer on an underlying layer in both the logic area and the memory area;
forming a second dielectric cap layer on the first dielectric cap layer only in the memory area, the first dielectric cap layer including a lower-K material than that of the second dielectric cap layer;
forming a bottom electrode contact (BEC) through the first dielectric cap layer and the second dielectric cap layer;
forming an MRAM stack on the BEC;
wherein the second dielectric cap layer surrounds an upper portion of the BEC.