US 12,464,730 B2
Method of forming capacitors through wafer bonding
Biswajeet Guha, Hillsboro, OR (US); Mauricio Manfrini, Heverlee (BE); Noriyuki Sato, Palo Alto, CA (US); James David Clarkson, El Sobrante, CA (US); Abel Fernandez, Berkeley, CA (US); Somilkumar J. Rathi, San Jose, CA (US); Niloy Mukherjee, San Ramon, CA (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Aug. 12, 2023, as Appl. No. 18/448,918.
Application 18/448,918 is a continuation of application No. 18/448,852, filed on Aug. 11, 2023.
Application 18/448,852 is a continuation in part of application No. 18/167,816, filed on Feb. 10, 2023, granted, now 11,765,908.
Prior Publication US 2024/0276735 A1, Aug. 15, 2024
Int. Cl. H10B 53/30 (2023.01); H01L 23/00 (2006.01); H10B 51/20 (2023.01); H10B 53/20 (2023.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01)
CPC H10B 53/30 (2023.02) [H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 24/80 (2013.01); H10B 51/20 (2023.02); H10B 53/20 (2023.02); H10D 1/042 (2025.01); H10D 1/043 (2025.01); H10D 1/682 (2025.01); H10D 1/692 (2025.01); H10D 1/716 (2025.01); H10D 30/0415 (2025.01); H10D 30/701 (2025.01); H10D 64/033 (2025.01); H10D 64/689 (2025.01); H01L 2224/05541 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/80931 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/04953 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method of fabricating a device, the method comprising:
forming a multi-layer stack above a first substrate, the multi-layer stack comprising a non-linear polar material having form ABC, wherein A and B are two different cations, and wherein C is oxygen or nitrogen;
forming a first conductive layer on the multi-layer stack;
annealing the multi-layer stack;
forming a transistor above a second substrate;
forming a second conductive layer above a terminal of the transistor;
bonding the first conductive layer with the second conductive layer;
removing the first substrate by at least a mechanical process or an etch process; and
patterning the multi-layer stack to form a memory device.