| CPC H10B 53/20 (2023.02) [G11C 5/025 (2013.01); G11C 5/10 (2013.01); G11C 11/221 (2013.01); G11C 11/4023 (2013.01); H10B 12/02 (2023.02); H10B 12/34 (2023.02)] | 20 Claims |
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1. A memory device, comprising:
a vertical transistor comprising a semiconductor body extending in a first direction, the semiconductor body comprising a doped source, a doped drain, and a channel portion;
a storage unit coupled to a first terminal, the first terminal being one of the source and the drain; and
a bit line extending in a second direction perpendicular to the first direction and in contact with a second terminal, the second terminal being another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body,
wherein:
the protrusion of the semiconductor body is connected with a body line that continuously extends in a third direction perpendicular to the first and second directions;
the second terminal comprises a first portion that directly contacts a sidewall of the bit line, and a second portion that directly contacts a bottom surface of the bit line;
a gate dielectric in a gate structure of the vertical transistor covers a sidewall of a base of the semiconductor body connected with the protrusion, and a dielectric layer is arranged on the bit line at a side opposite to the second portion of the second terminal, and in the third direction, a width of the dielectric layer is approximately equal to a width of the bit line, and a width of the first terminal and a thickness of the gate dielectric are approximately equal to widths of the bit line, the first portion of the second terminal, and the protrusion;
a projection of the bit line and a projection of the second terminal overlap on a plane perpendicular to the first direction, and the projection of the bit line and a projection of the first terminal overlap on the plane; and
the bit line is separated from the channel portion of the semiconductor body by the second terminal.
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