US 12,464,727 B2
Ferroelectric memory device
Gabjin Nam, Seoul (KR); Bongjin Kuh, Suwon-si (KR); Musarrat Hasan, Sejong-si (KR); Geonju Park, Suwon-si (KR); and Yongho Ha, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 25, 2022, as Appl. No. 18/049,366.
Claims priority of application No. 10-2021-0164865 (KR), filed on Nov. 25, 2021.
Prior Publication US 2023/0165012 A1, May 25, 2023
Int. Cl. H10B 51/30 (2023.01); H10B 51/20 (2023.01); H10D 30/60 (2025.01); H10D 30/69 (2025.01); H10D 64/68 (2025.01)
CPC H10B 51/30 (2023.02) [H10B 51/20 (2023.02); H10D 30/60 (2025.01); H10D 30/701 (2025.01); H10D 64/681 (2025.01); H10D 64/689 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A ferroelectric memory device comprising:
a channel layer on a substrate;
a mold insulating layer on the substrate;
an interface layer on the channel layer;
a high dielectric layer on the interface layer;
a ferroelectric layer on the high dielectric layer; and
a gate electrode layer on the ferroelectric layer,
a gate barrier layer between the gate electrode layer and the ferroelectric layer,
wherein the gate barrier layer is in contact with the mold insulating layer and the gate electrode layer, and
wherein the high dielectric layer and the ferroelectric layer comprise phases of different crystal structures.