US 12,464,726 B2
Three-dimensional memory device and method
Feng-Cheng Yang, Zhudong Township (TW); Meng-Han Lin, Hsinchu (TW); Han-Jong Chia, Hsinchu (TW); Sheng-Chen Wang, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 10, 2024, as Appl. No. 18/631,842.
Application 17/874,908 is a division of application No. 17/018,114, filed on Sep. 11, 2020, granted, now 11,647,634, issued on May 9, 2023.
Application 18/631,842 is a continuation of application No. 17/874,908, filed on Jul. 27, 2022, granted, now 11,985,830.
Claims priority of provisional application 63/052,505, filed on Jul. 16, 2020.
Prior Publication US 2024/0284679 A1, Aug. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 51/20 (2023.01); G11C 5/06 (2006.01); G11C 11/22 (2006.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01)
CPC H10B 51/20 (2023.02) [G11C 5/06 (2013.01); G11C 11/223 (2013.01); H10D 30/0415 (2025.01); H10D 30/701 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
filling a first trench and first recesses along sidewalls of the first trench with a first conductive material and a first dielectric material, the first dielectric material being a single dielectric material filling each part of the first trench that is not filled by the first conductive material;
after the filling the first trench, filling a second trench and second recesses along sidewalls of the second trench with a second conductive material and a second dielectric material;
etching the first conductive material and the second conductive material; and
after the etching the first conductive material and the second conductive material, depositing a channel material into the first trench.