US 12,464,724 B2
Memory arrays, and methods of forming memory arrays
Changhan Kim, Boise, ID (US); and Gianpietro Carnevale, Bottanuco (IT)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Nov. 10, 2023, as Appl. No. 18/506,327.
Application 18/506,327 is a division of application No. 17/746,671, filed on May 17, 2022, granted, now 11,832,447.
Application 17/746,671 is a division of application No. 16/987,187, filed on Aug. 6, 2020, granted, now 11,362,103, issued on Jun. 14, 2022.
Application 16/987,187 is a division of application No. 16/177,220, filed on Oct. 31, 2018, granted, now 10,770,472, issued on Sep. 8, 2020.
Prior Publication US 2024/0081074 A1, Mar. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/35 (2023.01); G06F 3/06 (2006.01); G11C 8/14 (2006.01); G11C 16/08 (2006.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/35 (2023.02) [G06F 3/0688 (2013.01); G11C 8/14 (2013.01); G11C 16/08 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A memory array, comprising:
a vertical stack of alternating insulative levels and wordline levels;
channel material extending vertically along the stack;
conductive gate regions within the wordline levels; the gate regions having substantially parabolic noses extending outwardly toward the channel material; and
memory cell structures along the wordline levels and located between the channel material and the parabolic noses of the gates.