US 12,464,722 B2
Three-dimensional type NAND memory device
Tatsufumi Hamada, Nagoya Aichi (JP); Yosuke Mitsuno, Yokkaichi Mie (JP); Tomohiro Kuki, Yokkaichi Mie (JP); and Yusuke Morikawa, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 16, 2022, as Appl. No. 17/842,411.
Claims priority of application No. 2022-037175 (JP), filed on Mar. 10, 2022.
Prior Publication US 2023/0292518 A1, Sep. 14, 2023
Int. Cl. H10B 43/35 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/35 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a stacked film including a plurality of electrode layers separated from each other in a first direction;
a first insulator provided on a first part of a side face of the stacked film at a predetermined height in the first direction;
a second insulator provided on a second part of the side face of the stacked film and a side face of the first insulator at the predetermined height;
a charge storage layer provided on a side face of the second insulator;
a third insulator provided on a side face of the charge storage layer; and
a semiconductor layer provided on a side face of the third insulator,
wherein the first insulator has an outer peripheral side face having a first curvature radius and an inner peripheral side face having a second curvature radius larger than the first curvature radius.