US 12,464,720 B2
Memory device with insulating pillar in staircase region and method of forming the same
Chia-Tze Huang, Hsing-Chu (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Apr. 19, 2023, as Appl. No. 18/302,806.
Prior Publication US 2024/0357811 A1, Oct. 24, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 23/60 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 23/60 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate having a memory array region and a staircase region;
a first stacked structure disposed on the substrate in the memory array region, wherein the first stacked structure comprises a plurality of first dielectric layers and a plurality of gates stacked alternately;
a second stacked structure disposed on the substrate in the staircase region, wherein the second stacked structure comprises a plurality of second dielectric layers and a plurality of stairs stacked alternately;
a channel structure penetrating through the first stacked structure in the memory array region;
an insulating pillar, penetrating through the second stacked structure in the staircase region;
a through via penetrating through the insulating pillar in the staircase region; and
a conductive layer surrounding a sidewall of the insulating pillar.