| CPC H10B 43/27 (2023.02) [H01L 21/32155 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 15 Claims |

|
1. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductor material;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, conducting material of a lowest of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier;
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising insulating material; and horizontally-elongated lines in the conductor material between the laterally-spaced memory blocks, the horizontally-elongated lines being of different composition from the conductor material that is laterally-between the horizontally-elongated lines; and
wherein an uppermost portion of the horizontally-elongated lines comprises conductively-doped semiconductive material having one of a primary n-type or p-type conductivity-producing dopant therein, at least the uppermost portion of the horizontally-elongated lines comprising a secondary dopant of different composition from that of the primary dopant.
|