US 12,464,717 B2
Semiconductor memory device and a manufacturing method of the semiconductor memory device
Jae Young Oh, Icheon-si (KR); and Joong Gyu Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 28, 2022, as Appl. No. 17/731,787.
Claims priority of application No. 10-2021-0150102 (KR), filed on Nov. 3, 2021.
Prior Publication US 2023/0137896 A1, May 4, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5283 (2013.01); H10B 41/27 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a plurality of conductive patterns and a plurality of second interlayer insulating layers arranged alternately with each other under a first interlayer insulating layer;
a doped semiconductor layer including an amorphous area overlapping the first interlayer insulating layer and a crystalline area overlapping the first interlayer insulating layer with the amorphous area interposed between the first interlayer insulating layer and the crystalline area;
a channel layer contacting the doped semiconductor layer and passing through the first interlayer insulating layer, the plurality of second interlayer insulating layers, and the plurality of conductive patterns; and
a memory layer between each of the conductive patterns and the channel layer,
a bit line over the channel layer and electrically connected to the channel layer;
a peripheral circuit structure over the bit line; and
a conductive bonding pad between the bit line and the peripheral circuit structure, and connecting the bit line and the peripheral circuit structure.