US 12,464,716 B2
NAND cell structure with charge trap cut
Chang Seok Kang, Santa Clara, CA (US); Tomohiko Kitajima, San Jose, CA (US); Gill Yong Lee, San Jose, CA (US); Balasubramanian Pranatharthiharan, San Jose, CA (US); and Mukund Srinivasan, Fremont, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Nov. 14, 2022, as Appl. No. 18/055,058.
Claims priority of provisional application 63/281,781, filed on Nov. 22, 2021.
Prior Publication US 2023/0164993 A1, May 25, 2023
Int. Cl. H10B 43/20 (2023.01); G11C 5/06 (2006.01); H10B 43/35 (2023.01)
CPC H10B 43/20 (2023.02) [G11C 5/063 (2013.01); H10B 43/35 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of memory cells formed around a memory hole extending through a memory stack on a substrate, the memory stack comprising a plurality of word lines and corresponding plurality of dielectric material layers alternatingly arranged to form the memory stack, each of the plurality of memory cells comprising a blocking oxide layer, a charge trap layer, and a tunnel oxide layer,
wherein the blocking oxide layer and the charge trap layer are confined by the dielectric materials layers in each of the plurality of memory cells, wherein the tunnel oxide layer extends continuously in the memory hole, and wherein the charge trap layer is confined between the tunnel oxide layer and the word line in each of the plurality of memory cells and has a first thickness on a top portion and a second thickness on a center portion, the first thickness different than the second thickness, and has a vertical height that is identical to a distance between the dielectric material layers; and
a filled slit extending through the memory stack adjacent to the memory hole.