US 12,464,715 B2
Semiconductor device
Keitaro Inoue, Yokkaichi Mie (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 1, 2022, as Appl. No. 17/901,506.
Claims priority of application No. 2022-039500 (JP), filed on Mar. 14, 2022.
Prior Publication US 2023/0292502 A1, Sep. 14, 2023
Int. Cl. H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/832 (2025.01)
CPC H10B 41/35 (2023.02) [H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 30/0227 (2025.01); H10D 30/601 (2025.01); H10D 30/6741 (2025.01); H10D 30/751 (2025.01); H10D 30/798 (2025.01); H10D 62/832 (2025.01); H10D 62/8325 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a transistor having a first diffusion region and a second diffusion region provided in the substrate, a gate insulating film provided over the substrate between the first diffusion region and the second diffusion region, and a gate electrode positioned on the gate insulating film;
a well region positioned between the first diffusion region and the second diffusion region in a first direction parallel to the substrate and including a channel region; and
an internal layer positioned in the substrate, wherein the internal layer has a first concentration of germanium and carbon higher than a second concentration of germanium and carbon of a region between the first diffusion region and the second diffusion region, wherein the well region positioned between the internal layer and the gate insulating layer in a second direction perpendicular to the substrate.