US 12,464,714 B2
Semiconductor device having non-continuous wall structure surrounding a stacked gate structure including a conductive layer disposed between segmented portions of the wall structure
Chien-Hsuan Liu, Tainan (TW); Chiang-Ming Chuang, Changhua (TW); Chih-Ming Lee, Tainan (TW); Kun-Tsang Chuang, Miaoli County (TW); Hung-Che Liao, Tainan (TW); Chia-Ming Pan, Tainan (TW); and Hsin-Chi Chen, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 31, 2024, as Appl. No. 18/429,264.
Application 18/429,264 is a continuation of application No. 16/740,499, filed on Jan. 13, 2020, granted, now 11,925,017.
Application 16/740,499 is a continuation of application No. 15/054,100, filed on Feb. 25, 2016, granted, now 10,535,670, issued on Jan. 14, 2020.
Prior Publication US 2024/0172434 A1, May 23, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/68 (2025.01); H01L 21/3213 (2006.01); H10B 41/10 (2023.01); H10B 41/30 (2023.01); H10B 41/42 (2023.01); H10B 41/47 (2023.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01)
CPC H10B 41/30 (2023.02) [H01L 21/32135 (2013.01); H10B 41/10 (2023.02); H10B 41/42 (2023.02); H10B 41/47 (2023.02); H10D 30/0411 (2025.01); H10D 30/683 (2025.01); H10D 30/6892 (2025.01); H10D 64/035 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of stacks and a stacked gate structure over a substrate, wherein the stacks are arranged along both a first direction and a second direction perpendicular to the first direction, and the stacks are extended continuously along the first direction and segmented in the second direction; and
a first conductive layer over the substrate, extending along the first direction and between segmented portions of the stacks along the second direction.