| CPC H10B 41/27 (2023.02) [H01L 21/3205 (2013.01); H01L 21/4763 (2013.01); H01L 21/70 (2013.01); H10B 12/0387 (2023.02); H10B 41/10 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); G11C 16/0483 (2013.01)] | 20 Claims |

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1. Memory circuitry comprising strings of memory cells, comprising:
memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region, the insulative tiers and the conductive tiers of the memory blocks extending from the memory-array region into a stair-step region;
individual of the memory blocks in the stair-step region comprising a flight of operative stairs, individual of the operative stairs comprising one of the conductive tiers;
at least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region having their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials; and
walls that are individually laterally between the immediately-laterally-adjacent memory blocks in the memory-array region, the walls not being laterally-adjacent said flights of operative stairs, the walls individually comprising an end portion that is in the stack comprising the two vertically-alternating different-composition insulative materials.
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