| CPC H10B 12/488 (2023.02) [H10B 12/50 (2023.02)] | 20 Claims |
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1. An apparatus, comprising:
a substrate;
a memory cell region provided over the substrate;
a first peripheral region provided over the substrate and adjacent to the memory cell region;
a second peripheral region provided over the substrate, the memory cell region arranged between the first peripheral region and the second peripheral region; and
first, second, third, fourth and fifth word-lines each extending in parallel across the memory cell region and the first peripheral region in numerical order;
first, third and fifth contacts on edge portions of the first, third and fifth word-lines, respectively, in the first peripheral region; and
second and fourth contacts on edge portions of the second and fourth word-lines, respectively, in the second peripheral region,
wherein, in the first peripheral region, an offcut of the second word-line is interposed between the edge portion of the first word-line where the first contact overlaps and the edge portion of the third word-line where the third contact overlaps,
wherein, in the first peripheral region, no offcut of the fourth word-line is interposed in a wiring-nonexistent region between the edge portion of the third word-line where the third contact overlaps and the edge portion of the fifth word line where the fifth contact overlaps.
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