US 12,464,703 B2
3D horizontal DRAM with in-situ bridge
Mark I. Gardner, Cedar Creek, TX (US); and H. Jim Fulford, Marianna, FL (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Sep. 16, 2022, as Appl. No. 17/946,690.
Claims priority of provisional application 63/310,205, filed on Feb. 15, 2022.
Prior Publication US 2023/0262956 A1, Aug. 17, 2023
Int. Cl. H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10B 12/30 (2023.02) [H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate,
wherein each DRAM cell unit comprises a respective transistor, a respective capacitor and a respective bridge structure,
each bridge structure is configured to electrically couple the respective transistor to the respective capacitor,
each capacitor is elongated in a horizontal direction parallel to the working surface of the substrate and adjacent to and co-planar with the respective transistor in the horizontal direction, and
each bridge structure comprises salicide material.