US 12,464,702 B2
Three-dimensional dynamic random-access memory (3D DRAM) gate all-around (GAA) design using stacked Si/SiGe
Sony Varghese, Manchester-by-the-Sea, MA (US); and Fredrick David Fishburn, Aptos, CA (US)
Assigned to APPLIED MATERIALS, INC., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Dec. 29, 2021, as Appl. No. 17/564,486.
Claims priority of provisional application 63/179,090, filed on Apr. 23, 2021.
Prior Publication US 2022/0344339 A1, Oct. 27, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/30 (2023.02) [H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 12/482 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A method of forming a three-dimensional dynamic random-access memory (3D DRAM) structure, comprising:
forming at least one wordline feature in a first stack comprising a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, wherein the wordline feature comprises:
vertically etching a first pattern of holes through the first stack;
filling the first pattern of holes with a silicon germanium fill having a concentration of germanium similar to a concentration of germanium in the plurality of c-SiGe layers;
vertically etching a plurality of isolation slots through the first stack, splitting the silicon germanium fill in each of the first pattern of holes;
filling the plurality of isolation slots with a dielectric material to form an isolation layer between the silicon germanium fill;
etching the silicon germanium fill and the plurality of c-SiGe layers to form a plurality of gate silicon channels comprising portions of the plurality of c-Si layers; and
depositing a layer of conductive material that wraps around the plurality of gate silicon channels.