	US 12,464,700 B2
	Method of manufacturing semiconductor structure
Jie Bai, Hefei (CN); and Kang You, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 18, 2022, as Appl. No. 17/651,577.
Application 17/651,577 is a continuation of application No. PCT/CN2021/111890, filed on Aug. 10, 2021.
Claims priority of application No. 202110469981.4 (CN), filed on Apr. 28, 2021.
Prior Publication US 2022/0352175 A1, Nov. 3, 2022
Int. Cl. H10B 12/00 (2023.01)

CPC H10B 12/05 (2023.02) [H10B 12/50 (2023.02)]

13 Claims

1. A method of manufacturing a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises multiple array regions and a non-array region, the non-array region surrounds the array regions and comprises a core region and a periphery region, the core region is located on a periphery of the array regions and also arranged between the array regions, the periphery region is located on a periphery of the core region, and the core region comprises a first transistor region and a second transistor region, the peripheral region comprises a third transistor region and a fourth transistor region;

forming a mask layer on the substrate;

removing the mask layer on the non-array region;

forming a first oxide layer on the non-array region;

removing the first oxide layer on the first transistor region, to expose a top surface of the first transistor region;

forming an epitaxial layer on the exposed top surface of the first transistor region;

removing the first oxide layer only on the second transistor region and keeping the first oxide layer on the third transistor region and the fourth transistor region; and

forming a second oxide layer on the second transistor region and the epitaxial layer and also on a remaining first oxide layer on the third transistor region and the fourth transistor region;

wherein a thickness of the first oxide layer is greater than a thickness of the second oxide layer.