US 12,464,699 B2
Semiconductor structure and forming method thereof
Liang Li, Singapore (SG); Chunyu Wong, Clifton Park, NY (US); John H Zhang, Altamont, NY (US); Yanzun Li, Lagrangeville, NY (US); Huang Liu, Mechanicville, NY (US); Yuan Lung Lin, Zhubei (TW); Haijiang Yuan, Shanghai (CN); and Chung-Chiang Lin, Qonglin (TW)
Assigned to HEFECHIP CORPORATION LIMITED, Hong Kong (CN)
Filed by HeFeChip Corporation Limited, Hong Kong (CN)
Filed on Dec. 27, 2022, as Appl. No. 18/088,944.
Prior Publication US 2024/0215218 A1, Jun. 27, 2024
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/0387 (2023.02) [H10B 12/056 (2023.02); H10B 12/36 (2023.02); H10B 12/373 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a doped substrate layer, a buried oxide layer and a device layer;
forming at least one deep trench in the substrate, wherein each deep trench extends through the device layer and the buried oxide layer into the doped substrate layer;
forming a corresponding deep trench capacitor in each deep trench, wherein the deep trench capacitor comprises a node dielectric layer covering a part of an inner surface of the deep trench, and an inner electrode filled in the deep trench, and wherein the node dielectric layer separates the inner electrode from the doped substrate layer;
etching the device layer and the inner electrode to expose the underlying buried oxide layer, wherein the etched device layer forms at least one fin, and a portion of the etched inner electrode forms a fin contact connected to the corresponding fin;
forming a word line isolation layer on the substrate, wherein the fin is exposed from the word line isolation layer;
forming a plurality of word lines on the substrate, wherein at least one of the word lines intersects the at least one fin and provides a gate of a transistor on a surface of each fin and at least one of the word lines passes over and is separated by the word line isolation layer from the inner electrodes;
forming spacers on sidewalls of each word line, wherein the word line isolation layer covers a surface of a portion of the inner electrode between the buried oxide layer and the fin contact; and
performing an epitaxial process to form a source/drain epitaxial structure on the surface of the fin on opposite sides of the gate.