US 12,464,696 B2
Static random access memory device with stacked FETs
Huimei Zhou, Albany, NY (US); Carl Radens, LaGrangeville, NY (US); Chen Zhang, Santa Clara, CA (US); Junli Wang, Slingerlands, NY (US); and Miaomiao Wang, Albany, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 22, 2023, as Appl. No. 18/212,826.
Prior Publication US 2024/0431087 A1, Dec. 26, 2024
Int. Cl. H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/85 (2025.01)
CPC H10B 10/12 (2023.02) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first stacked field effect transistor (FET) structure in a first device area, the first stacked FET structure comprising a first pull down (PD) transistor, and a first pull up (PU) transistor disposed over the first PD transistor;
a first metal gate that is shared by the first PD transistor and the first PU transistor; and
an oxygen blocking layer formed on the first metal gate.